Allwinner /D1H /TWI[3] /TWI_DRV_CTRL

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Interpret as TWI_DRV_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (disable)twi_drv_en 0 (normal)soft_reset 0timeout_n0 (be)twi_sta0 (ok)tran_result 0 (send)read_tran_mode 0 (restart)restart_mode 0 (idle)start_tran

soft_reset=normal, twi_sta=be, restart_mode=restart, read_tran_mode=send, start_tran=idle, tran_result=ok, twi_drv_en=disable

Description

TWI_DRV Control Register

Fields

twi_drv_en

0 (disable): undefined

1 (enable): undefined

soft_reset

Software reset

0 (normal): undefined

1 (reset): undefined

timeout_n

Timeout number

twi_sta

TWI status

0 (be): bus error

1 (t_s9sc): Timeout when sending the 9th SCL clock

8 (sct): START condition transmitted

16 (rsct): Repeated START condition transmitted

24 (awbt_ar): Address + Write bit transmitted, ACK received

32 (awbt_anr): Address + Write bit transmitted, ACK not received

40 (dbtm_ar): Data byte transmitted in master mode, ACK received

48 (dbtm_anr): Data byte transmitted in master mode, ACK not received

56 (al_a_db): Arbitration lost in address or data byte

64 (arbt_ar): Address + Read bit transmitted, ACK received

72 (arbt_anr): Address + Read bit transmitted, ACK not received

80 (dbrm_ar): Data byte received in master mode, ACK received

88 (dbrm_anr): Data byte received in master mode, ACK not received

tran_result

Transition result

0 (ok): undefined

1 (fail): undefined

read_tran_mode

Read transition mode

0 (send): undefined

1 (not_send): undefined

restart_mode

Restart mode

0 (restart): undefined

1 (stop_restart): undefined

start_tran

Start transmission

0 (idle): undefined

1 (start): undefined

Links

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